Why is the semiconductor process so complicated?

Front-end process of semiconductor manufacturing

  Technical stream netizens often discuss why it is so difficult to manufacture domestic chips. In fact, the front-end process, back-end process and packaging of semiconductors are a complex process. Let’s take a look today.

Although there are 500 to 1000 (or even more) processes in the front-end process of semiconductors, the process is very simple

  First, a silicon wafer (Silicon Wafer) with a diameter of 200 to 300 mm is used as a substrate, and the following prescribed processes are performed (repeated 30 to 50 times, or even more): cleaning → film formation → lithography patterning → Etching → polishing (Ashing) or cleaning → inspection. In addition to the above processes, there are ion implantation, heat treatment, CMP and other processes.
  Through the previous process, 3D structures such as transistors, capacitors, and wires are formed on the silicon wafer. In addition, about 1000 chips (Chip) are simultaneously formed on the silicon wafer. The main equipment used in the previous process, which accounts for a relatively high proportion are coating and developing equipment (Coater & Developer, 92%), heat treatment equipment (also known as “vertical diffusion furnace”, 93%), single-chip cleaning equipment ( 63%) and batch cleaning equipment (86%), length measuring SEM (80%), etc.

Proportion of companies that use main materials in the previous process

  Asian companies account for a very high proportion of products such as silicon wafers, various photoresists, various CMP slurries, and various high-purity solutions. In Europe and the United States, how did the four European and American companies, AMAT (Applied Materials), Lam Research (Lam, Fanlin Group), KLA (Klei), and ASML (ASM) develop equipment? First of all, according to the market (Marketing), they grasp the demand (Needs), all kinds of equipment have science components in the initial research and development stage. Under the guidance of demand and technology, according to a strong top-down leadership, the entire equipment is constructed, and it is mostly presented in a modular form.
  At various stages of developing the equipment, simulation experiments are carried out. At the same time, technology and skills are “software” and integrated into the equipment. Finally, the above elements are brought together to produce equipment with global standards.
  Therefore, it can be seen that the “hard and strong” “contract spirit” of European and American societies has been vividly reflected. In general, most Asian equipment manufacturers “tailor-made” equipment for each semiconductor manufacturer, while European and American equipment manufacturers basically only produce one type of equipment with global standards.
  This is the reason why Asian companies occupy a high proportion of liquids, fluids and other materials with irregular shapes, while European and American manufacturers have a high proportion of vacuum equipment using light, electron beam (Beam) and plasma.
  Europeans and Americans are the first in theory. In the early stages of development, there is sufficient discussion before a policy is fixed. On this basis, create rules (Rule), plot (Story), logic (Logic). On the other hand, the subordinates of European and American technicians are clumsy and their level of experimentation is not high.

3D packaging in the back-end process of semiconductor manufacturing

  Next we discuss the post-process. With the advent of the era of 3D packaging (3D Packing, hereinafter referred to as “3D IC”), there has been a change between the front-end process and the back-end process (package).
  Around 2010, the semiconductor front-end process was in an absolute advantage. Among them, lithography technicians are the so-called “sweet pastry”, and even the following remarks appeared: “Without lithography, there will be no etching”; “As long as lithography is done well, transistors will be automatically made through subsequent processes. “.

Transfer of previous and subsequent processes

  However, in the cutting-edge semiconductors of modern society, various Foundry foundries (such as TSMC, etc.), IDM (Integrated Device Manufacturer, vertically integrated) manufacturers such as Intel and Samsung Electronics, OSAT (Outsourced Semiconductor Assembly and Test, outsourced semiconductor product packaging and test) manufacturers are racing to start developing 3D ICs.
  In the face of fierce market competition, the pursuit of “light, thin, short, small” dimensions and multi-functionality of end consumer electronic products has never stopped. At present, the focus of research and development in the packaging industry is to maximize the use of thickness. 3D IC technology is currently the only one. The key technology that can meet the above requirements is to use 3D IC stacking, TSV, TSV and other technologies to integrate the chip into the state with the best performance and the smallest volume.
  As far as 3D IC R&D is concerned, packaging design is the first to be developed. Chips such as SoC (System on Chip), GPU, and DRAM integrated into 3D ICs have been commercialized. To produce the above “commodities”, the technical elements of the previous process are required.
  In the front-end process, about 1,000 chips (Chip) are formed on a single wafer, and in the latter-stage process, through the cutting (Dicing) process, each chip (Chip) is cut out and packaged on the IC carrier. On the board, various tests are carried out, and the product is finally completed.
  Different from the previous process, the organic substrate (usually an organic substrate used to mount chips, is said to be different depending on the application and company) is relatively complicated in the latter process. That is, there is no global standard in the back-end process like the silicon wafer (Silicon Wafer) in the front-end process, so it is difficult to understand the back-end process.
Is miniaturization the most important process

  In addition, compared with the Technology Node of the previous process, there is a three-digit difference in the Design Rule of the latter process (the former process is nano-level, and the latter process is micro-level).

  For now, TSMC has started mass production of N5 (5-nanometer) nodes in the front-end process, while the design rules for organic substrates used in the back-end process are still at 5 microns. In addition, TSMC has started producing chips using its N3 (3-nanometer scale) manufacturing process. As usual, the chip contract manufacturer and its partners will take several quarters to perfect the technology and design before moving into high-volume manufacturing (HVM).
  TSMC has started trial production of N3 chips at its Fab 18 in the Science Park near Tainan, and the first batch of N3 chips manufactured by TSMC will ship in early 2023 due to the cycle time of the new process exceeding 100 days. TSMC’s N3 manufacturing technology is a next-generation node for foundries designed for smartphone and high-performance computing (HPC) applications, a departure from TSMC’s usual strategy of addressing mobile designs first. The new process will aggressively use “over 20 layers” of extreme ultraviolet lithography (EUVL) and substantially improve the existing N5 node. TSMC promises 10% to 15% performance improvement (at the same power and transistor count), up to 30% power reduction (at the same clock and complexity), up to 70% logic density gain and up to 20% SRAM density gain.
  Those who are fully immersed in the front-end process of the idea of ​​”only miniaturization is the most important process” may see this situation and think that “the semiconductor back-end process is also at the level of MEMS (Micro Electro Mechanical Systems).” In fact, this idea is not rigorous. If the design rules of organic substrates in the latter process can closely follow the miniaturization development of the previous process, then the final packaged product can obviously be sold at a high price, which is very beneficial to sales.
  As far as the process of the back-end process is concerned, there are both OSAT (Outsourced Semiconductor Assembly and Testing, outsourced semiconductor product packaging and testing) packaging, and chip factories (such as Intel) packaging by themselves. In order to facilitate the reader’s understanding, we assume that all Packaged by OSAT.
  (1) First, Intel decides which company’s substrate the chip will be packaged on, and Intel decides the raw material of the substrate.
  (2) Substrate material manufacturers such as Ajinomoto Fine-Techno and Mitsubishi Gas Chemicals selected by Intel supply substrate materials to substrate manufacturers selected by Intel (Ifei Dentsu, Shinko Electric).
  (3) Yifei Electric and Shinko Electric produce organic substrates according to Intel’s specifications, and then ship the substrates to OSAT manufacturers such as ASE and Amkor.
  (4) OSAT purchases all kinds of equipment and materials for the back-end process, such as DISCO (Disco) cutting equipment (Dicer) and so on.
  (5) Intel will then hand over the wafers (Wafer) completed in the previous process to OSAT.
  (6) OSAT uses various equipment and materials in the back-end process to package and test various final products for Intel.
  As mentioned above, after the coordination and cooperation of various equipment in the front and rear processes, after the process is completed, a processor (Processor) was born.

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